What is RISC-V ?
RISC-V is an open source instruction set architecture. Based on reduced instruction set computers. Which means RISC-V provides CPU architecture which is free to use and the CPU vendor does not need to provide a license fee in order to use this architecture. The need for open source hardware architecture arises years after using few of the available architectures. There are many advantages of open source hardware architecture, a few of them are mentioned below.
- No licensing fee for the architecture.
- Easy customisation of the architecture based on the clients requirements.
- Can update the architecture with changing technology.
- Saves time.
- Provide enhancement to existing architectures.
RISC started in 1980 to reduce the number of instructions needed in a CPU. As we know the chipset market is increasing year on year with roughly 7 billion chipsets used worldwide as of 2020 in many devices like mobile phones, cameras, smart meters, sensors, drones, wifi, laptops, cloud servers the list goes on and on. And the number of devices used is expected to grow 3-4 times more in the next 5 – 10 years. Hence with growing demand for more and more technology and innovation. A push for open source hardware architecture is increasing.
An Instruction is usually an assembly language code that tells the CPU what to do since each CPU has a bunch of register and memory locations architecture vendor provides instructions to control the CPU. For example move a to b This is a simple instruction which tells the CPU to move the contents of register a to b. So there are 1000’s of instructions that are made available by the vendor who designs the architecture. Now a good CPU architecture will provide almost 99% perfect architecture and assembly instructions to operate the CPU. But even then due to the changing technology, innovations and use cases in the real work. The architecture vendor cannot guarantee a 100% instructions set that works perfectly. Due to limited reasons. Let’s take a look at one of the x86 assembly programs.
_start: mov ax, 1 ; system call for write function
mov di, 1 ; file handle 1 is stdout for display
mov si, message ; address of string to output to move
mov dx, 13 ; number of bytes to move
syscall ; invoke system to do the write operation
mov ax, 60 ; system call for exit here
xor di, di ; exit from code 0
syscall ; invoke OS system to exit
message: db “Hello to the World”, 15 ; Add the newline at the end
The above program contains as you can see instructions and these instructions will be converted into binary format logic 0 or 1 before they can run on the CPU. But in the modern world we do not see these instruction sets. Today the world uses high level languages like C, C++, Java, .net python and so on. With an increasing number of applications developers just learn one of the high level languages to develop their applications. And do not worry about the underlying architecture or instruction set.
In reality these high level languages are compiled and converted into machine level language called the assembly language by the compilers developed by the architecture vendors. Hence there is a slight gap between high level developers and the architecture vendors. In order to fill this gap RISC-V made the architecture open source hardware architecture. So that developers from any level high level and low level can work closely to understand the behaviour of the CPU. An example is we have seen many times our phone, laptop freezes or hangs. By closing the gap between engineers and developers RISC-V can achieve high success in the throughput.
Why is RISC-V gaining popularity ?
There are many reasons why it is gaining popularity; a few of them are mentioned below.
- Open source architecture Since the architecture is open many developers can see how the 1s and 0s are flowing in the CPU. and suggest any improvements or issues that occur during the experimental phase or testing phase. And add new IP as technology, innovation advances over time.
- Trailer the architecture specific the clients workload with the past architecture it was impossible to tailor the architecture even if there was a need to do so. With open source architecture now they can tailor however they want as per their workload. Which helps semiconductor manufacturers to save time as they need not wait for new innovation or new architecture to be released by the architecture vendors.
- Mostly 90% of the cloud servers use Intel which means it is more easily hacked by attackers. Intel releases patches to stop these attacks from hackers cause a huge hit in the performance of the servers. But with RISC-V architecture every vendor can have their own version of security embedded in the architecture making it difficult for attackers.
- Cost of using the architecture is completely free. As we are aware of the growth of technology and innovation, everyone is bound to use a smart device in some way either in a car or in home or in the office or around us. When semiconductor vendors pay for a license of architecture it increases the overall cost of the end device. With open source architecture silicon vendors can provide smart devices necessary in day to day use at a reasonable price.
List of RISC-V evaluation boards.
There are many RISC-V based chipset some of them are SoC some of them are FPGA chipset. Below table specifies some of the RISC-V architecture based CPU chipsets.
|FE310-G002||SiFive||Product page||E31||RV32IMAC||RTOS||HiFive1 Rev B|
|Freedom U540||SiFive||Product page||U54 (4 cores), E51 (1 management core)||RV64GC (application cores), RV64IMAC (management core)||Linux||HiFive Unleashed development board|
|GAP8||GreenWaves Technologies||Product page||PULP / 1 + 8 RI5CY||RV32IMC (+ Priviledged and custom ISA extensions)||RTOS||GAPuino development board|
|K210||Kendryte||Product page, Datasheet, GitHub||K210||RV64GC||Linux||KD233 development board, Sipeed MAIX/M1 development boards|
|RV32M1||NXP||Reference Manual and Datasheet||RI5CY + Zero RI5CY + Arm Cortex M4F + Arm Cortex M0+||RV32IMC||RTOS||VEGAboard|
|RavenRV32||efabless||Datasheet, GitHub||PicoRV32||RV32IMAC||RTOS||RavenRV32 DevKit|
|PolarFire SoC||Microchip||Product Page, IDE with Renode platform||U54 (4 cores), E51 (management core)||RV64GC(U54), RV64IMAC(E51)||Linux||HiFive Unleashed Expansion Board, PolarFire SoC|
|GD32VF103||GigaDevice||Product listing,Datasheets||Bumblebee Core||RV32IMAC||RTOS||GD32VF103V-EVAL, Longan Nano etc.|
The above table does not specify all the FPGA, VHDL hardware.
RISC-V vs ARM vs x86 Comparison.
Bellow is the list of comparison between custom ISA, Licensed ISA and Open source ISA.
|Custom ISA||Licensed ISA||Licensed ISA with architecture license||Open-Source ISA|
|Design Flexibility||High||Low||Moderate to high||High|
|License Fees||None||$0 to millions||$0 to millions||None|
|Royalty Fees||None||0 to a few %||0 to a few %||0 to a few %|
|Available Software||None to little||Moderate to extensive||Moderate to extensive||Little to moderate|
|Processor Cores||Custom||Standard||Standard to custom||Custom or standard|
|Hardware Engineering Costs||High||Low||Low to moderate||High|
|Software Engineering Costs||High||Low to moderate||Low to moderate||Moderate to high|
|DevelopmentTime||Long||Short||Short to moderate||Long|
|Manufacturability Risk||High||Low||Low to moderate||Moderate to high|
|Time-to-Market||Long||Short||Short to moderate||Moderate to high|